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An overview of Babak's dry EEG sensor

In mid-90s, Alizadeh-Taheri et al. produced an insulated electrode designed specifically for EEG and built using conventional semiconductor fabrication equipment [1].  Several interesting features were incorporated including multiple electrode contacts for redundancy, electrostatic discharge (ESD) circuitry, and an application-specific ultra-low noise amplifier.  Silicon nitride (Si₃N₄) was selected from materials common to thin-film capacitors as the insulating material because of its excellent resistance to chloride corrosion and ease of deposition [2].  Other materials considered were silicon monoxide, silicon dioxide and tantalum pentoxide.  Silicon monoxide and silicon dioxide were rejected because of their reactivity with chloride ions.  Tantalum pentoxide had been shown previously to be impervious to chloride corrosion [3], but the temperatures required for proper deposition would have complicated fabrication.  In this device, DC bias is set by the source through the resistance of the insulating layer (20-40 MΩ) [2].

The necessity of an ultra-low noise amplifier is particular to EEG recording. Unlike ECG, which is measured in mV, EEG is measured in μV, orders of magnitude smaller. This poses a problem related to our preference for high amplifier input impedance. To satisfy this requirement, the input stage was designed using metal-oxide-semiconductor FETs (MOSFETs). However, with this type of transistor, given the low-level signals of EEG, one needs to carefully manage noise from the amplifier, in particular flicker or 1/f noise.

1/f noise is so-named because its associated power spectral density (PSD) is inversely proportional to frequency. In MOSFETs, 1/f noise is attributed to the random trapping and detrapping of charge carriers in oxide defects at or near the semiconductor-insulator interface [4,5]. This trapping-detrapping process alters the channel carrier density. In addition, the trapped charges act as Coulombic scattering sites, inducing fluctuations into the channel mobility. Consideration of these two factors has been shown to accurately model 1/f noise in standard MOSFET transistors.

There are a number of ways to deal with this type of noise. The brute force approach is to create MOSFETs which by design have sufficiently low 1/f noise. MOSFETs are typically operated in saturation [6] for which the 1/f input referred noise is well-described by [5]

S Vg ≅ q 2 C ox 2 N ot WL 1 f MathType@MTEF@5@5@+=feaafeart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4uamaaBaaaleaacaWGwbGaam4zaaqabaGccqGHfjcqdaWcaaqaaiaadghadaahaaWcbeqaaiaaikdaaaaakeaacaWGdbWaa0baaSqaaiaad+gacaWG4baabaGaaGOmaaaaaaGcdaWcaaqaaiaad6eadaWgaaWcbaGaam4BaiaadshaaeqaaaGcbaGaam4vaiaadYeaaaWaaSaaaeaacaaIXaaabaGaamOzaaaaaaa@4602@ .

(1.1)

Here, q MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamyCaaaa@36E3@  is the electron charge, C ox MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4qamaaBaaaleaacaWGVbGaamiEaaqabaaaaa@38D2@  the gate oxide capacitance per unit area, and W MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4vaaaa@36C9@  and L MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamitaaaa@36BE@  the width and length of the channel respectively. N ot MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamOtamaaBaaaleaacaWGVbGaamiDaaqabaaaaa@38D9@  , the equivalent density of oxide traps, is defined by

N ot [c m −2 ]= kT N t (E) γ MathType@MTEF@5@5@+=feaafeart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamOtamaaBaaaleaacaWGVbGaamiDaaqabaGccaGGBbGaam4yaiaad2gadaahaaWcbeqaaiabgkHiTiaaikdaaaGccaGGDbGaeyypa0ZaaSaaaeaacaWGRbGaamivaiaad6eadaWgaaWcbaGaamiDaaqabaGccaGGOaGaamyraiaacMcaaeaacqaHZoWzaaaaaa@4707@

(1.2)

where N t (E)[c m −3 e V −1 ] MathType@MTEF@5@5@+=feaafeart1ev1aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamOtamaaBaaaleaacaWG0baabeaakiaacIcacaWGfbGaaiykaiaacUfacaWGJbGaamyBamaaCaaaleqabaGaeyOeI0IaaG4maaaakiaadwgacaWGwbWaaWbaaSqabeaacqGHsislcaaIXaaaaOGaaiyxaaaa@4330@  is the density of oxide traps per unit volume and unit energy, kT MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4Aaiaadsfaaaa@37B6@  is the Boltzmann constant times the temperature, and γ MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaeq4SdCgaaa@3794@  is a parameter related to the effective mass of the tunneling carrier and the barrier height of the trap. (1.1) and (1.2) suggest three possibilities: (1) reduce the temperature, (2) select a process minimizing the density of oxide traps, and (3) maximize the width and length of the channel. Alizadeh-Taheri elected to implement (2) and (3), choosing p-doped MOS (PMOS) and fabricating channels with large dimensions [2]. It is well-established that the effective density of oxide traps in PMOS transistors is much lower than n-doped MOS (NMOS) transistors. As a result, S Vg MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4uamaaBaaaleaacaWGwbGaam4zaaqabaaaaa@38B8@  in PMOS devices can be several orders of magnitude lower than equivalent NMOS devices [2,5]. With regards to channel size, Alizadeh-Taheri set W=220 MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaam4vaiabg2da9iaaikdacaaIYaGaaGimaaaa@3A01@  mm and L=10 MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamitaiabg2da9iaaigdacaaIWaaaaa@3939@  mm. For comparison, transistors in an Intel Pentium 4 processor have dimensions nearly a thousand times smaller, e.g., L=60 MathType@MTEF@5@5@+=feaafeart1ev1aqatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaGaamitaiabg2da9iaaiAdacaaIWaaaaa@393E@  nm [7].

References
[1] B. Alizadeh-Taheri, R. L. Smith, and R. T. Knight, "An active, microfabricated, scalp electrode array for EEG recording," Sensors and Actuators A, vol. 54, pp. 606-611, 1996.

[2] B. Alizadeh-Taheri, "An Active Micromachined Scalp Electrode Array for EEG Signal Recording," Ph.D. dissertation, University of California Davis, Davis, CA 1994.

[3] C. H. Lagow, K. J. Sladek, and P. C. Richardson, "Anodic insulated tantalum oxide electrocardiograph electrodes," IEEE Trans Biomed Eng, vol. 18, no. 2, pp. 162-4, Mar 1971.

[4] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Transactions on Electron Devices, vol. 37, no. 3, pt.1, pp. 654-65, 1990.

[5] Y. Nemirovsky, I. Brouk, and C. G. Jakobson, "1/f noise in CMOS transistors for analog applications," IEEE Transactions on Electron Devices, vol. 48, no. 5, pp. 921-7, 2001.

[6] B. Razavi, Design of analog CMOS integrated circuits. Boston, MA: McGraw-Hill, 2001.

[7] S. Thompson, M. Alavi, M. Hussein, P. Jacob, C. Kenyon, P. Moon, M. Prince, S. Sivakumar, S. Tyagi, and M. Bohr, "130nm Logic Technology Featuring 60nm Transistors, Low-K Dielectrics, and Cu Interconnects," Intel Technology Journal: Semiconductor Technology and Manufacturing, vol. 6, no. 2, pp. 1-13, 16 May 2002.

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